This invention generally relates to plasma etching of semiconductor features and more particularly to a method for improving a trench etching profile at a trench/via interface in a dual damascene process.
During the formation of semiconductor devices it is often required that the conductive layers be interconnected through holes in an insulating layer also referred to as an inter-metal or inter-level dielectric (IMD/ILD) layer. Such holes are commonly referred to as contact holes, i.e., when the hole extends through an insulating layer to an active device area, or vias, i.e., when the hole extends through an insulating layer between two conductive layers. The profile of a via or contact hole is of particular importance since that it exhibits specific electrical characteristics when the contact hole or via is filled with a conductive material. Typically, the holes are high aspect ratio holes, meaning that the ratio of length to width is at least greater than about 1 and may extend up to about 4 or higher. Such holes are typically formed by a plasma etch process where complex chemical processes result in relatively higher etching rates in one direction versus another, known as anisotropic etching. The relative anisotropicity or selectivity of the etching process will in turn determine the etching profile of an etched hole and consequently its aspect ratio. As semiconductor structures are inevitably driven to smaller sizes, successful etching of higher aspect ratio holes with uniform profiles is becoming more important and more difficult.
In anisotropically etching contact or via holes (openings), plasmas containing fluorocarbons or hydrofluorocarbons including oxygen and nitrogen are typically optimized in various steps in a plasma etching process to selectively etch through the various layers of materials included in a multi-layer semiconductor device. For example, it is typically required to selectively etch through an oxide containing layer, for example an IMD layer to a desired depth. Frequently, etching stop layers, for example, nitride or silicon carbide, are formed in the substrate for several reasons including providing a material non-selective to an etching chemistry to protect an underlying layer and to provide a dissimilar material for plasma etching endpoint detection to reliably etch to a particular depth. In addition, an etching stop layer functions as a hard mask resistant to an etching chemistry to reduce undesired isotropic etching in overlying layers.
For example, the damascene process is a well known semiconductor fabrication method for forming electrical interconnects between layers by forming vias and overlying connecting trench lines. In a typical dual damascene process, a via opening is first etched into an insulating layer also known as an inter-metal or inter-level dielectric (IMD/ILD) layer. The insulating layer is typically formed over a metal or conductive layer. After a series of photolithographic steps defining via openings and trench openings, the via openings and the trench openings are filled with a metal (e.g., Al, Cu) to form vias and trench lines, respectively. The excess metal above the trench level is then removed and the uppermost layer planarized usually by a chemical-mechanical polishing (CMP) process.
Referring to FIG. 1A, for example, is a typical dual damascene structure following via opening etching and trench etching. In a typical dual damascene processing approach it has been useful to form an etching stop layer between the trench layer and the via layer forming the trench/via interface. Following this approach, a substrate is provided, for example, having a conductive area 12A formed in an insulating layer 12B. Overlying the conductive area 12A and insulating layer 12B is formed a first etching stop layer 14A and a via insulating layer 16A for etching a via therein. Overlying the via insulating layer 16A is a second etching stop layer 14B. One approach in forming the dual damascene structure is to form a trench insulating layer 16B, followed by a third etching stop layer 14C which is photolithographically patterned and etched to form a via opening e.g., 20A that extends through the substrate to the conductive area 12A. Following formation of the via opening 20A, the photolithographic patterning process is repeated to etch a trench opening e.g., 20B formed substantially over the via opening e.g., 20A. The first, second, and third etching stop layers 14A, 14B, and 14C are typically formed of a nitride or carbide including for example, silicon nitride (e.g., Si3N4), silicon carbide (e.g., SiC), and silicon oxynitride (e.g., SiON). In a typical plasma etching process the etching stop layers e.g., 14A, 14B, and 14C are advantageously used to detect an etching depth, for example, by optical detection of etched plasma species and provide an increased etching selectivity, e.g., 14B and 14C, while etching the insulating layer to maintain a uniform etching profile. For example, when etching the trench opening e.g., 20B, the etching stop layer 14B protects the via opening 20A from isotropic etching when the trench etching depth reaches the etching stop layer 14B.
One shortcoming of the above approach is the presence of relatively high dielectric constant (e.g.,  greater than 6.5) nitride or carbide etching stop layers which undesirably add to the overall capacitance of the multi-layer structure thereby increasing parasitic electrical contributions to signal delay times. Another drawback of forming etching stop layers between the insulating layers (IMD/ILD layers), which are frequently porous to reduce the dielectric constant of the insulating layer, is that poor adhesion between the etching stop and IMD layer results leading to reduced multi-layer strength and in many cases, peeling during subsequent chemical mechanical polishing processes. In an effort to overcome these shortcomings and drawbacks, another approach to dual damascene processing has been to eliminate etching stop layers including at the trench/via interface e.g., 14B, in the processing scheme. In this approach, referring to FIG. 1B. only one insulating layer is provided e.g., 16C for etching both the via opening 20A and trench opening 20B. In this approach, the trench etching process typically proceeds for a predetermined period of time in contrast with end-point detection provided by an etching stop layer, e.g., 14B in FIG. 1A. With the many etching variable involved in plasma processing, it has proven difficult to achieve consistent trench etching results by using a predetermined process window (etching time) for trench etching.
Another troublesome drawback to this approach is the unintended etching of the via opening 20A at the trench/via interface, for example, forming a faceted, tapered opening in the via profile e.g., 20C where the via opening profile increases in diameter at the trench/via interface. Non-uniform profiles such as the faceted profile 20C cause an undesirable departure from electrical property design specifications and thereby compromise the quality and reliability of the semiconductor device.
These and other shortcomings demonstrate a need in the semiconductor processing art to develop a method for improving a dual damascene plasma etching process to achieve more uniform etching profiles while enhancing plasma etching endpoint detection.
It is therefore an object of the invention to a method for improving a dual damascene plasma etching process to achieve more uniform etching profiles while enhancing plasma etching endpoint detection while overcoming other shortcomings and deficiencies in the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a plasma etching method for improving an etching profile.
In one embodiment, the method includes providing a substrate including an oxide containing insulating layer in a multilayer semiconductor device; providing a patterned photoresist layer exposing an uppermost layer of the substrate for anisotropically plasma etching a first opening; anisotropically plasma etching through a thickness of at least a portion of the substrate to form the first opening; blanket depositing an etching stop liner to cover at least a portion of the sidewalls of the first opening; patterning according to a photolithographic process for etching a second opening at least partially overlying and encompassing the first opening; and, anisotropically plasma etching through at least another portion of the thickness of the substrate including the first opening to form a second opening at least partially overlying a remaining portion of the first opening.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.